HD64F3687GHV Datasheet, PDF (172/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
9.2.2 Port Data Register 2 (PDR2)
PDR2 is a general I/O port data register of port 2.
Initial
Bit
Bit Name Value R/W Description
7 to 5 
All 1

Reserved
These bits are always read as 1.
4
P24
0
R/W PDR2 stores output data for port 2 pins.
3
P23
0
2
P22
0
1
P21
0
0
P20
0
R/W If PDR2 is read while PCR2 bits are set to 1, the value
R/W ^{stored in PDR2 is read. If PDR2 is read while PCR2 bits}
are cleared to 0, the pin states are read regardless of the
R/W _{value stored in PDR2.}
R/W
9.2.3 Port Mode Register 3 (PMR3)
PMR3 selects the CMOS output or NMOS open-drain output for port 2.
Initial
Bit
Bit Name Value R/W Description
7 to 5 
All 0

Reserved
These bits are always read as 0.
4
POF24 0
3
POF23 0
R/W When the bit is set to 1, the corresponding pin is cut off
R/W ^{by PMOS and it functions as the NMOS open-drain}
output. When cleared to 0, the pin functions as the CMOS
output.
2 to 0 
All 1

Reserved
These bits are always read as 1.
Rev. 3.00 Sep. 10, 2007 Page 138 of 528
REJ09B0216-0300