HD64F3687GHV Datasheet, PDF (129/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Power-Down Modes
Initial
Bit
Bit Name Value
6
STS2
0
5
STS1
0
4
STS0
0
3
NESEL 0
2 to 0 
All 0
R/W
R/W
R/W
R/W
R/W

Description
Standby Timer Select 2 to 0
These bits set the wait time from when the external clock
oscillator starts functioning until the clock is supplied, in
shifting from standby mode, subactive mode, or subsleep
mode, to active mode or sleep mode. During the wait
time, this LSI automatically selects the on-chip oscillator
clock as its system clock and counts the number of wait
states. Select a wait time of 6.5 ms (oscillation
stabilization time) or longer, depending on the operating
frequency. Table 6.1 shows the relationship between the
STS2 to STS0 values and the wait time.
When using an external clock, set the wait time to be
100 µs or longer.
These bits also set the wait states for external oscillation
stabilization when system clock is switched from the on-
chip oscillator clock to the external clock by user
software.
The relationship between Nwait (number of wait states for
oscillation stabilization) and Nstby (number of wait states
for recovering to the standby mode) is as follows.
Nstby ≤ Nwait ≤ 2 × Nstby
Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch clock
signal (φ ) and the external clock pulse generator
W
generates the oscillator clock (φ_OSC). This bit selects the
sampling frequency of the oscillator clock when the watch
clock signal (φ ) is sampled. When φ = 4 to 20 MHz,
W
OSC
clear NESEL to 0.
0: Sampling rate is φ_OSC/16
1: Sampling rate is φ_OSC/4
Reserved
These bits are always read as 0.
Rev. 3.00 Sep. 10, 2007 Page 95 of 528
REJ09B0216-0300