HD64F3687GHV Datasheet, PDF (86/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Initial
Bit
Bit Name Value R/W Description
6
IRRTA 0
R/W RTC Interrupt Request Flag
[Setting condition]
When the RTC counter value overflows
[Clearing condition]
When IRRTA is cleared by writing 0
5, 4 
All 1

Reserved
These bits are always read as 1.
3
IRRI3
0
R/W IRQ3 Interrupt Request Flag
[Setting condition]
When IRQ3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI3 is cleared by writing 0
2
IRRI2
0
R/W IRQ2 Interrupt Request Flag
[Setting condition]
When IRQ2 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI2 is cleared by writing 0
1
IRRI1
0
R/W IRQ1 Interrupt Request Flag
[Setting condition]
When IRQ1 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI1 is cleared by writing 0
0
IRRl0
0
R/W IRQ0 Interrupt Request Flag
[Setting condition]
When IRQ0 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI0 is cleared by writing 0
Rev. 3.00 Sep. 10, 2007 Page 52 of 528
REJ09B0216-0300