HD64F3687GHV Datasheet, PDF (95/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
Normal mode operation
Interrupt is accepted
Interrupt level
decision and wait ^Instruction
for end of instruction ^prefetch
Internal
processing
Interrupt
request signal
Stack access
Internal Prefetch instruction of
Vector fetch _{processing interrupt handling routine}
φ
Internal
address bus
Internal
read signal
Internal
write signal
Internal data
bus (16 bits)
(1)
(3)
(5)
(6)
(8)
(2)
(4)
(1)
(7)
(9)
(9)
(10)
(1) Instruction prefetch address (Instruction is not executed.
(7) CCR
Address is saved as PC contents, becoming return address.) (8) Vector address
(2), (4) Instruction code (Instruction is not executed.)
(9) Start address of interrupt handling routine (contents of vector)
(3) Instruction prefetch address (Instruction is not executed.)
(10) First instruction of interrupt handling routine.
(5) SP - 2
(6) SP - 4
Advanced mode operation
Interrupt is accepted
Interrupt level
decision and wait
Instruction Internal
prefetch processing
for end of instruction
Interrupt
request signal
Stack access
Vector fetch
Internal Prefetch instruction of
processing interrupt handling routine
φ
Internal
address bus
Internal
read signal
Internal
write signal
Internal
data bus
(1)
(3)
High level
(2)
(4)
(5)
(7)
(9)
(11)
(13)
(6)
(8)
(10)
(12)
(14)
(1) Instruction prefetch address (Instruction is not executed.
Address is saved as PC contents, becoming return address.)
(2), (4) Instruction code (Instruction is not executed.)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP - 2
(7) SP - 4
(6), (8) Saved PC and CCR
(9), (11) Vector address
(10), (12) Start address of interrupt handling routine (contents of vector)
(13)
Start address of interrupt handling routine ((13), (10), (12))
(14)
First instruction of interrupt handling routine.
Figure 3.3 Interrupt Sequence
Rev. 3.00 Sep. 10, 2007 Page 61 of 528
REJ09B0216-0300