HD64F3687GHV Datasheet, PDF (125/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Clock Pulse Generator
5.6.2 Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown
in figure 5.19.
V_CL or V_SS
X₁
X₂
Open
Figure 5.19 Pin Connection when not Using Subclock
5.7 Prescaler
5.7.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. The outputs, which are
divided clocks, are used as internal clocks by the on-chip peripheral modules. Prescaler S is
initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode
and subsleep mode, the external clock oscillator stops. Prescaler S also stops and is initialized to
H'0000. It cannot be read from or written to by the CPU.
The outputs from prescaler S are shared by the on-chip peripheral modules. The division ratio can
be set separately for each on-chip peripheral module. In active mode and sleep mode, the clock
input to prescaler S is a system clock with the division ratio specified by bits MA2 to MA0 in
SYSCR2.
5.7.2 Prescaler W
Prescaler W is a 5-bit counter using a 32.768-kHz signal divided by 4 as its input clock. The
divided output is used for clock time base operation of the RTC. Prescaler W is initialized to H'00
by a reset, and starts counting on exit from the reset state. Even in standby mode, subactive mode,
or subsleep mode, prescaler W continues functioning.
Rev. 3.00 Sep. 10, 2007 Page 91 of 528
REJ09B0216-0300