HD64F3687GHV Datasheet, PDF (330/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 16 Serial Communication Interface 3 (SCI3)
16.3.8 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 16.3
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 16.4 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 16.3 and 16.4 are values in active (high-
speed) mode. Table 16.5 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 of SMR in clock synchronous mode. The values shown in table 16.5 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N=
φ
64 × 2^2n–1 × B
× 10⁶ – 1
Error
(%)
=

_(N
+
1)
φ
×
×
B
10⁶
× 64
×
2^2n–1
–1
× 100
[Clock Synchronous Mode]
N=
φ
8 × 2^2n–1 × B
× 10⁶ – 1
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CSK1 and CSK0 settings in SMR (0 ≤ n ≤ 3)
Rev. 3.00 Sep. 10, 2007 Page 296 of 528
REJ09B0216-0300