HD64F3687GHV Datasheet, PDF (70/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
2.6 Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φ_SUB). The period from a rising
edge
of
φ
or
φ
SUB
to
the
next
rising
edge
is
called
one
state.
A
bus
cycle
consists
of
two
states
or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
ø or ø_SUB
Internal address bus
Bus cycle
T₁ state
T₂ state
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
Rev. 3.00 Sep. 10, 2007 Page 36 of 528
REJ09B0216-0300