HD64F3687GHV Datasheet, PDF (355/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 16 Serial Communication Interface 3 (SCI3)
16.6.2 Multiprocessor Serial Data Reception
Figure 16.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI3 operations are the same as those in asynchronous mode.
Figure 16.18 shows an example of SCI3 operation for multiprocessor format reception.
Rev. 3.00 Sep. 10, 2007 Page 321 of 528
REJ09B0216-0300