HD64F3687GHV Datasheet, PDF (75/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 2 CPU
Example 2: The BSET instruction is executed for port 5.
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
• Prior to executing BSET instruction
P57
P56
P55
Input/output Input Input Output
Pin state
Low
level
High
level
Low
level
PCR5
0
0
1
PDR5
1
0
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P50
Output
Low
level
1
0
• BSET instruction executed instruction
BSET #0, @PDR5
The BSET instruction is executed for port 5.
• After executing BSET instruction
P57
P56
P55
Input/output Input Input Output
Pin state
Low
level
High
level
Low
level
PCR5
0
0
1
PDR5
0
1
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P50
Output
High
level
1
1
• Description on operation
1. When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
Rev. 3.00 Sep. 10, 2007 Page 41 of 528
REJ09B0216-0300