HD64F3687GHV Datasheet, PDF (311/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 Watchdog Timer
Initial
Bit
Bit Name Value R/W Description
2
WDON 1
R/W Watchdog Timer On
TCWD starts counting up when the WDON bit is set to 1
and halts when the WDON bit is cleared to 0. The
watchdog timer is enabled in the initial state. When the
watchdog timer is not used, clear the WDON bit to 0.
[Setting conditions]
• Reset
• When 1 is written to the WDON bit and 0 is written to
the B2WI bit while the TCSRWE bit = 1
[Clearing condition]
• When 0 is written to the WDON bit and 0 is written to
the B2WI bit while the TCSRWE bit = 1
1
B0WI
1
R/W Bit 0 Write Inhibit
This bit can be written to the WRST bit only when the
write value of the B0WI bit is 0. This bit is always read as
1.
0
WRST 0
R/W Watchdog Timer Reset
[Setting condition]
• When TCWD overflows and an internal reset signal is
generated
[Clearing conditions]
• Reset by the RES pin
• When 0 is written to the WRST bit and 0 is written to
the B0WI bit while the TCSRWE bit = 1
Rev. 3.00 Sep. 10, 2007 Page 277 of 528
REJ09B0216-0300