HD64F3687GHV Datasheet, PDF (18/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

16.4.3 Data Transmission ............................................................................................ 305
16.4.4 Serial Data Reception ....................................................................................... 307
16.5 Operation in Clock Synchronous Mode............................................................................ 311
16.5.1 Clock................................................................................................................. 311
16.5.2 SCI3 Initialization............................................................................................. 311
16.5.3 Serial Data Transmission .................................................................................. 312
16.5.4 Serial Data Reception (Clock Synchronous Mode) .......................................... 314
16.5.5 Simultaneous Serial Data Transmission and Reception.................................... 316
16.6 Multiprocessor Communication Function ........................................................................ 318
16.6.1 Multiprocessor Serial Data Transmission ......................................................... 319
16.6.2 Multiprocessor Serial Data Reception .............................................................. 321
16.7 Interrupts........................................................................................................................... 325
16.8 Usage Notes ...................................................................................................................... 326
16.8.1 Break Detection and Processing ....................................................................... 326
16.8.2 Mark State and Break Sending ......................................................................... 326
16.8.3 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ..................................................................... 326
16.8.4 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode......................................................................................... 327
Section 17 I²C Bus Interface 2 (IIC2).................................................................. 329
17.1 Features............................................................................................................................. 329
17.2 Input/Output Pins.............................................................................................................. 331
17.3 Register Descriptions........................................................................................................ 332
17.3.1 I²C Bus Control Register 1 (ICCR1) ................................................................. 332
17.3.2 I²C Bus Control Register 2 (ICCR2) ................................................................. 335
17.3.3 I²C Bus Mode Register (ICMR)........................................................................ 336
17.3.4 I²C Bus Interrupt Enable Register (ICIER) ....................................................... 338
17.3.5 I²C Bus Status Register (ICSR)......................................................................... 340
17.3.6
17.3.7
17.3.8
17.3.9
Slave Address Register (SAR).......................................................................... 343
I²C Bus Transmit Data Register (ICDRT)......................................................... 344
I²C Bus Receive Data Register (ICDRR).......................................................... 344
I²C Bus Shift Register (ICDRS)........................................................................ 344
17.4 Operation .......................................................................................................................... 345
17.4.1 I²C Bus Format.................................................................................................. 345
17.4.2 Master Transmit Operation ............................................................................... 346
17.4.3 Master Receive Operation................................................................................. 348
17.4.4 Slave Transmit Operation ................................................................................. 350
17.4.5 Slave Receive Operation................................................................................... 352
17.4.6 Clock Synchronous Serial Format .................................................................... 354
Rev. 3.00 Sep. 10, 2007 Page xvi of xxxii