HD64F3687GHV Datasheet, PDF (250/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
Initial
Bit
Bit Name value R/W Description
2
IOA2
0
R/W I/O Control A2 to A0
1
IOA1
0
R/W GRA is an output compare register:
0
IOA0
0
R/W 000: Disables pin output by compare match
001: 0 output by GRA compare match
010: 1 output by GRA compare match
011: Toggle output by GRA compare match
GRA is an input capture register:
100: Input capture to GRA at the rising edge
101: Input capture to GRA at the falling edge
11X: Input capture to GRA at both rising and falling edges
[Legend] X: Don't care.
TIORC: TIORC selects whether GRC or GRD is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORC
also selects the function of FTIOC or FTIOD pin.
Initial
Bit
Bit Name value R/W Description
7

1

Reserved
This bit is always read as 1.
6
IOD2
0
R/W I/O Control D2 to D0
5
IOD1
0
R/W GRD is an output compare register:
4
IOD0
0
R/W 000: Disables pin output by compare match
001: 0 output by GRD compare match
010: 1 output by GRD compare match
011: Toggle output by GRD compare match
GRD is an input capture register:
100: Input capture to GRD at the rising edge
101: Input capture to GRD at the falling edge
11X: Input capture to GRD at both rising and falling
edges
3

1

Reserved
This bit is always read as 1.
Rev. 3.00 Sep. 10, 2007 Page 216 of 528
REJ09B0216-0300