HD64F3687GHV Datasheet, PDF (247/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
13.3.7 Timer Counter (TCNT)
The timer Z has two TCNT counters (TCNT_0 and TCNT_1), one for each channel. The TCNT
counters are 16-bit readable/writable registers that increment/decrement according to input clocks.
Input clocks can be selected by bits TPSC2 to TPSC0 in TCR. TCNT0 and TCNT 1
increment/decrement in complementary PWM mode, while they only increment in other modes.
The TCNT counters are initialized to H'0000 by compare matches with corresponding GRA, GRB,
GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function). When
the TCNT counters overflow, an OVF flag in TSR for the corresponding channel is set to 1. When
TCNT_1 underflows, an UDF flag in TSR is set to 1. The TCNT counters cannot be accessed in 8-
bit units; they must always be accessed as a 16-bit unit. TCNT is initialized to H'0000.
13.3.8 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD)
GR are 16-bit registers. Timer Z has eight general registers (GR), four for each channel. The GR
registers are dual function 16-bit readable/writable registers, functioning as either output compare
or input capture registers. Functions can be switched by TIORA and TIORC.
The values in GR and TCNT are constantly compared with each other when the GR registers are
used as output compare registers. When the both values match, the IMFA to IMFD flags in TSR
are set to 1. Compare match outputs can be selected by TIORA and TIORC.
When the GR registers are used as input capture registers, the TCNT value is stored after detecting
external signals. At this point, IMFA to IMFD flags in the corresponding TSR are set to 1.
Detection edges for input capture signals can be selected by TIORA and TIORC.
When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the
values in TIORA and TIORC are ignored. Upon reset, the GR registers are set as output compare
registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8-bit units;
they must always be accessed as a 16-bit unit.
Rev. 3.00 Sep. 10, 2007 Page 213 of 528
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