HD64F3687GHV Datasheet, PDF (302/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
13.6 Usage Notes
1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated
in the T₂ state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not
performed. Figure 13.52 shows the timing in this case.
TCNT write cycle
T1
T2
φ
TCNT address
WTCNT
(internal write signal)
Counter clear signal
TCNT
N
H'0000
Clearing has priority.
Figure 13.52 Contention between TCNT Write and Clear Operations
2. Contention between TCNT Write and Increment Operations: If increment is done in T₂ state of
a TCNT write cycle, TCNT writing has priority. Figure 13.53 shows the timing in this case.
Rev. 3.00 Sep. 10, 2007 Page 268 of 528
REJ09B0216-0300