HD64F3687GHV Datasheet, PDF (82/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
3.2 Register Descriptions
Interrupts are controlled by the following registers.
• Interrupt edge select register 1 (IEGR1)
• Interrupt edge select register 2 (IEGR2)
• Interrupt enable register 1 (IENR1)
• Interrupt enable register 2 (IENR2)
• Interrupt flag register 1 (IRR1)
• Interrupt flag register 2 (IRR2)
• Wakeup interrupt flag register (IWPR)
3.2.1 Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to
IRQ0.
Initial
Bit
Bit Name Value R/W Description
7
NMIEG 0
R/W NMI Edge Select
0: Falling edge of NMI pin input is detected
1: Rising edge of NMI pin input is detected
6 to 4 
All 1

Reserved
These bits are always read as 1.
3
IEG3
0
R/W IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
2
IEG2
0
R/W IRQ2 Edge Select
0: Falling edge of IRQ2 pin input is detected
1: Rising edge of IRQ2 pin input is detected
1
IEG1
0
R/W IRQ1 Edge Select
0: Falling edge of IRQ1 pin input is detected
1: Rising edge of IRQ1 pin input is detected
0
IEG0
0
R/W IRQ0 Edge Select
0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected
Rev. 3.00 Sep. 10, 2007 Page 48 of 528
REJ09B0216-0300