HD64F3687GHV Datasheet, PDF (317/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 14-Bit PWM
15.3 Register Descriptions
The 14-bit PWM has the following registers.
• PWM control register (PWCR)
• PWM data register U (PWDRU)
• PWM data register L (PWDRL)
15.3.1 PWM Control Register (PWCR)
PWCR selects the conversion period.
Initial
Bit
Bit Name Value R/W
7 to 1 
All 1

0
PWCR0 0
R/W
[Legend]
tφ: Period of PWM clock input
Description
Reserved
These bits are always read as 1, and cannot be modified.
Clock Select
0: The input clock is φ/2 (tφ = 2/φ)
 The conversion period is 16384/φ, with a minimum
modulation width of 1/φ
1: The input clock is φ/4 (tφ = 4/φ)
 The conversion period is 32768/φ, with a minimum
modulation width of 2/φ
15.3.2 PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and
PWDRL are 14-bit write-only registers, with the upper 6 bits assigned to PWDRU and the lower 8
bits to PWDRL. When read, all bits are always read as 1.
Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed
if word access is performed. When 14-bit data is written in PWDRU and PWDRL, the contents
are latched in the PWM waveform generator and the PWM waveform generation data is updated.
When writing the 14-bit data, the order is as follows: PWDRL to PWDRU.
PWDRU and PWDRL are initialized to H'C000.
Rev. 3.00 Sep. 10, 2007 Page 283 of 528
REJ09B0216-0300