HD64F3687GHV Datasheet, PDF (23/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figures
Section 1 Overview
Figure 1.1 Block Diagram of H8/36079 Group and H8/36077 Group ........................................... 4
Figure 1.2 Pin Arrangement of H8/36079 Group and
H8/36077 Group (FP-64K, FP-64A) ............................................................................ 5
Section 2 CPU
Figure 2.1 Memory Map............................................................................................................... 11
Figure 2.2 CPU Registers ............................................................................................................. 12
Figure 2.3 Usage of General Registers ......................................................................................... 13
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 14
Figure 2.5 General Register Data Formats (1) .............................................................................. 16
Figure 2.5 General Register Data Formats (2) .............................................................................. 17
Figure 2.6 Memory Data Formats................................................................................................. 18
Figure 2.7 Instruction Formats...................................................................................................... 29
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 33
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 36
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 37
Figure 2.11 CPU Operation States................................................................................................ 38
Figure 2.12 State Transitions ........................................................................................................ 39
Figure 2.13 Example of Timer Configuration with Two Registers
Allocated to Same Address ....................................................................................... 40
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 57
Figure 3.2 Stack Status after Exception Handling ........................................................................ 59
Figure 3.3 Interrupt Sequence....................................................................................................... 61
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 62
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 63
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 68
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 69
Section 5 Clock Pulse Generator
Figure 5.1 Block Diagram of Clock Pulse Generator ................................................................... 71
Figure 5.2 State Transition of System Clock ................................................................................ 79
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled................................... 80
Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1)
(From On-Chip Oscillator Clock to External Clock) ................................................. 81
Rev. 3.00 Sep. 10, 2007 Page xxi of xxxii