HD64F3687GHV Datasheet, PDF (408/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 18 A/D Converter
18.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t_D) has passed after the ADST bit is set to 1, then
starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D
conversion time.
As indicated in figure 18.2, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 18.3.
In scan mode, the values given in table 18.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
t_D
t_SPL
t_CONV
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t_D: A/D conversion start delay time
t_SPL: Input sampling time
t_CONV: A/D conversion time
Figure 18.2 A/D Conversion Timing
Rev. 3.00 Sep. 10, 2007 Page 374 of 528
REJ09B0216-0300