HD64F3687GHV Datasheet, PDF (244/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
TCNT_0
TCNT_1
Normal phase
Active level
Counter phase
Initial
output
Active level
Reset synchronous PWM mode
Normal phase
Counter phase
Initial
output
Active level
Complementary PWM mode
Active level
Note: Write H'00 to TOCR to start initial outputs after stopping the counter.
Figure 13.4 Example of Outputs in Reset Synchronous PWM Mode
and Complementary PWM Mode
13.3.5 Timer Output Master Enable Register (TOER)
TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for
inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output
for timer Z.
Initial
Bit
Bit Name Value R/W Description
7
ED1
1
R/W Master Enable D1
0: FTIOD1 pin output is enabled according to the TPMR,
TFCR, and TIORC_1 settings
1: FTIOD1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOD1 pin is operated
as an I/O port).
6
EC1
1
R/W Master Enable C1
0: FTIOC1 pin output is enabled according to the TPMR,
TFCR, and TIORC_1 settings
1: FTIOC1 pin output is disabled regardless of the TPMR,
TFCR, and TIORC_1 settings (FTIOC1 pin is operated
as an I/O port).
Rev. 3.00 Sep. 10, 2007 Page 210 of 528
REJ09B0216-0300