HD64F3687GHV Datasheet, PDF (256/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
13.3.14 Interface with CPU
1. 16-bit register
TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in
an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be
accessed in a 16-bit unit. Figure 13.5 shows an example of accessing the 16-bit registers.
Internal data bus
H
C
P
L
Bus interface
U
Module data bus
TCNTH TCNTL
Figure 13.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits))
2. 8-bit register
Registers other than TCNT and GR are 8-bit registers that are connected internally with the
CPU in an 8-bit width. Figure 13.6 shows an example of accessing the 8-bit registers.
Internal data bus
H
C
P
L
Bus interface
U
Module data bus
TSTR
Figure 13.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits))
Rev. 3.00 Sep. 10, 2007 Page 222 of 528
REJ09B0216-0300