HD64F3687GHV Datasheet, PDF (27/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure 13.45 Example of Output Disable Timing of Timer Z by External Trigger .................... 263
Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 264
Figure 13.47 Example of Output Inverse Timing of Timer Z by Writing to POCR ................... 264
Figure 13.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 265
Figure 13.49 IMF Flag Set Timing at Input Capture .................................................................. 266
Figure 13.50 OVF Flag Set Timing ............................................................................................ 266
Figure 13.51 Status Flag Clearing Timing.................................................................................. 267
Figure 13.52 Contention between TCNT Write and Clear Operations....................................... 268
Figure 13.53 Contention between TCNT Write and Increment Operations ............................... 269
Figure 13.54 Contention between GR Write and Compare Match ............................................. 269
Figure 13.55 Contention between TCNT Write and Overflow................................................... 270
Figure 13.56 Contention between GR Read and Input Capture.................................................. 271
Figure 13.57 Contention between Count Clearing and Increment Operations
by Input Capture................................................................................................... 272
Figure 13.58 Contention between GR Write and Input Capture................................................. 273
Figure 13.59 When Compare Match and Bit Manipulation Instruction to TOCR
Occur at the Same Timing .................................................................................... 274
Section 14 Watchdog Timer
Figure 14.1 Block Diagram of Watchdog Timer ........................................................................ 275
Figure 14.2 Watchdog Timer Operation Example...................................................................... 279
Section 15 14-BIt PWM
Figure 15.1 Block Diagram of 14-Bit PWM .............................................................................. 281
Figure 15.2 Waveform Output by 14-Bit PWM ......................................................................... 284
Section 16 Serial Communication Interface 3 (SCI3)
Figure 16.1 Block Diagram of SCI3 ........................................................................................... 287
Figure 16.2 Data Format in Asynchronous Communication ...................................................... 303
Figure 16.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)............. 303
Figure 16.4 Sample SCI3 Initialization Flowchart ..................................................................... 304
Figure 16.5 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)........................................................................... 305
Figure 16.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode) ...................... 306
Figure 16.7 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)........................................................................... 307
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (1)...................... 309
Figure 16.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2)...................... 310
Figure 16.9 Data Format in Clock Synchronous Communication .............................................. 311
Figure 16.10 Example of SCI3 Transmission in Clock Synchronous Mode .............................. 312
Figure 16.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode) .................... 313
Rev. 3.00 Sep. 10, 2007 Page xxv of xxxii