HD64F3687GHV Datasheet, PDF (31/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Tables
Section 1 Overview
Table 1.1 Pin Functions ............................................................................................................ 6
Section 2 CPU
Table 2.1 Operation Notation ................................................................................................. 19
Table 2.2 Data Transfer Instructions....................................................................................... 20
Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 21
Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 22
Table 2.4 Logic Operations Instructions................................................................................. 23
Table 2.5 Shift Instructions..................................................................................................... 23
Table 2.6 Bit Manipulation Instructions (1)............................................................................ 24
Table 2.6 Bit Manipulation Instructions (2)............................................................................ 25
Table 2.7 Branch Instructions ................................................................................................. 26
Table 2.8 System Control Instructions.................................................................................... 27
Table 2.9 Block Data Transfer Instructions ............................................................................ 28
Table 2.10 Addressing Modes .................................................................................................. 30
Table 2.11 Absolute Address Access Ranges ........................................................................... 32
Table 2.12 Effective Address Calculation (1)........................................................................... 34
Table 2.12 Effective Address Calculation (2)........................................................................... 35
Section 3 Exception Handling
Table 3.1 Exception Sources and Vector Address .................................................................. 46
Table 3.2 Interrupt Wait States ............................................................................................... 60
Section 4 Address Break
Table 4.1 Access and Data Bus Used ..................................................................................... 66
Section 5 Clock Pulse Generator
Table 5.1 Crystal Resonator Parameters ................................................................................. 89
Section 6 Power-Down Modes
Table 6.1 Operating Frequency and Waiting Time................................................................. 96
Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode
due to Interrupt...................................................................................................... 101
Table 6.3 Internal State in Each Operating Mode................................................................. 102
Section 7 ROM
Table 7.1 Setting Programming Modes ................................................................................ 117
Table 7.2 Boot Mode Operation ........................................................................................... 119
Rev. 3.00 Sep. 10, 2007 Page xxix of xxxii