HD64F3687GHV Datasheet, PDF (421/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits
t_PWON
Vcc
Vpor
Vss
RES
Vss
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 19.3 Operational Timing of Power-On Reset Circuit
19.3.2 Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detection) Circuit:
Figure 19.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is kept
enabled during the LSI's operation.
When the power-supply voltage falls below the Vreset voltage (the value selected by the LVDSEL
bit: Typ. = 2.3 V or 3.6 V), the LVDR circuit clears the LVDRES signal to 0, and resets prescaler
S. The low-voltage detection reset state remains in place until a power-on reset is generated. When
the power-supply voltage rises above the Vreset voltage (Typ. = 3.6 V) regardless of LVDSEL bit
setting) again, the LVDR circuit sets the LVDRES signal to 1 and prescaler S starts counting.
When 131,072 clock (φ) cycles have been counted, the internal reset signal is released. In this
case, the LVDSEL bit in LVDCR is initialized (the Vreset voltage: Typ. = 3.6 V) though the
VDDII bit is not initialized.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
Rev. 3.00 Sep. 10, 2007 Page 387 of 528
REJ09B0216-0300