HD64F3687GHV Datasheet, PDF (101/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 4 Address Break
4.1.2 Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Initial
Bit
Bit Name Value
7
ABIF
0
6
ABIE
0
5 to 0 
All 1
R/W
R/W
R/W

Description
Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
Reserved
These bits are always read as 1.
4.1.3 Break Address Registers (BARE, BARH, BARL)
Settings of the address where an address-break interrupt is to be generated are made in the break
address registers (BAR: BARE*, BARH and BARL). For microcontrollers that support normal-
mode operation, BAR is a 16-bit readable/writable register with initial value H'FFFF. For
microcontrollers that support advanced-mode operation, BAR is a 24-bit readable/writable register
with the initial value H'FFFFFF. When setting an instruction execution cycle as the address break
condition, set BAR to the address of the first byte of the instruction.
Note: * BARE is only provided for microcontrollers that support advanced-mode operation.
4.1.4 Break Data Registers (BDRH, BDRL)
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in BDRH
for byte access. For word access, the data bus used depends on the address. See section 4.1.1,
Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
Rev. 3.00 Sep. 10, 2007 Page 67 of 528
REJ09B0216-0300