HD64F3687GHV Datasheet, PDF (366/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 I²C Bus Interface 2 (IIC2)
17.3 Register Descriptions
The I²C bus interface 2 has the following registers:
• I²C bus control register 1 (ICCR1)
• I²C bus control register 2 (ICCR2)
• I²C bus mode register (ICMR)
• I²C bus interrupt enable register (ICIER)
• I²C bus status register (ICSR)
• I²C bus slave address register (SAR)
• I²C bus transmit data register (ICDRT)
• I²C bus receive data register (ICDRR)
• I²C bus shift register (ICDRS)
17.3.1 I²C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I²C bus interface 2, controls transmission or reception, and selects
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Initial
Bit
Bit Name Value R/W Description
7
ICE
0
R/W I²C Bus Interface Enable
0: This module is halted. (SCL and SDA pins are set to
port function.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6
RCVD
0
R/W Reception Disable
This bit enables or disables the next operation when TRS
is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Rev. 3.00 Sep. 10, 2007 Page 332 of 528
REJ09B0216-0300