HD64F3687GHV Datasheet, PDF (367/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 I²C Bus Interface 2 (IIC2)
Initial
Bit
Bit Name Value R/W Description
5
MST
0
R/W Master/Slave Select
4
TRS
0
R/W Transmit/Receive Select
In master mode with the I²C bus format, when arbitration
is lost, MST and TRS are both reset by hardware,
causing a transition to slave receive mode. Modification
of the TRS bit should be made between transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data agree
with the slave address that is set to SAR and the eighth
bit is 1, TRS is automatically set to 1. If an overrun error
occurs in master mode with the clock synchronous serial
format, MST is cleared to 0 and slave receive mode is
entered.
Operating modes are described below according to MST
and TRS combination. When clock synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3
CKS3
0
R/W Transfer Clock Select 3 to 0
2
CKS2
0
1
CKS1
0
0
CKS0
0
R/W These bits should be set according to the necessary
R/W ^{transfer rate (see table 17.2) in master mode. In slave}
mode, these bits are used for reservation of the setup
R/W _{time in transmit mode. The time is 10 tcyc when CKS3 = 0}
and 20 t_cyc when CKS3 = 1.
Rev. 3.00 Sep. 10, 2007 Page 333 of 528
REJ09B0216-0300