HD64F3687GHV Datasheet, PDF (84/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
3.2.3 Interrupt Enable Register 1 (IENR1)
IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts.
Initial
Bit
Bit Name Value R/W Description
7
IENDT 0
R/W Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
6
IENTA 0
R/W RTC Interrupt Enable
When this bit is set to 1, RTC interrupt requests are
enabled.
5
IENWP 0
R/W Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
4

1

Reserved
This bit is always read as 1.
3
IEN3
0
R/W IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3 pin
are enabled.
2
IEN2
0
R/W IRQ2 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ2 pin
are enabled.
1
IEN1
0
R/W IRQ1 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ1 pin
are enabled.
0
IEN0
0
R/W IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0 pin
are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
Rev. 3.00 Sep. 10, 2007 Page 50 of 528
REJ09B0216-0300