HD64F3687GHV Datasheet, PDF (292/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
Figure 13.40 shows an operation example in which GRA has been designated as an input capture
register, and buffer operation has been designated for GRA and GRC.
Counter clearing by input capture B has been set for TCNT, and falling edges have been selected
as the FIOCB pin input capture input edge. And both rising and falling edges have been selected
as the FIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in GRA upon the occurrence of
input capture A, the value previously stored in GRA is simultaneously transferred to GRC. The
transfer timing is shown in figure 13.41.
TCNT value
H'0180
H'0160
Counter is cleared by the input capture B
H'0005
H'0000
Time
FTIOB
FTIOA
GRA
GRC
GRB
H'0005
H'0160
H'0005
H'0160
H'0180
Input capture A
Figure 13.40 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register)
Rev. 3.00 Sep. 10, 2007 Page 258 of 528
REJ09B0216-0300