HD64F3687GHV Datasheet, PDF (131/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Power-Down Modes
6.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Initial
Bit
Bit Name Value
7
SMSEL 0
6
LSON
0
5
DTON
0
4
MA2
0
3
MA1
0
2
MA0
0
1
SA1
0
0
SA0
0
[Legend] X: Don't care.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Sleep Mode Selection
Low Speed on Flag
Direct Transfer on Flag
These bits select the mode to enter after the execution of
a SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6.2.
Active Mode Clock Select 2 to 0
These bits select the operating clock frequency in active
and sleep modes. The operating clock frequency
changes to the set frequency after the SLEEP instruction
is executed.
0XX: φ_OSC
100: φ_OSC/8
101: φ /16
OSC
110: φ /32
OSC
111: φ_OSC/64
Subactive Mode Clock Select 1 and 0
These bits select the operating clock frequency in
subactive and subsleep modes. The operating clock
frequency changes to the set frequency after the SLEEP
instruction is executed.
00: φ /8
W
01: φ_W/4
1X: φ_W/2
Rev. 3.00 Sep. 10, 2007 Page 97 of 528
REJ09B0216-0300