HD64F3687GHV Datasheet, PDF (138/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Power-Down Modes
6.2.3 Subsleep Mode
In subsleep mode, operation of the CPU and on-chip peripheral modules other than RTC is halted.
As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and
some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as
before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1
or the requested interrupt is disabled in the interrupt enable register. After subsleep mode is
cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is
made to subactive mode when the bit is 1. After the time set in bits STS2 to STS0 in SYSCR1 has
elapsed, a transition is made to active mode.
When the RES pin is driven low in standby mode, the on-chip oscillator starts functioning. Once
the oscillator starts, the system clock is supplied to the entire chip. The RES pin must be kept low
for the rated period set by the power-on reset circuit, until the oscillator stabilizes. If the RES pin
is driven high after the oscillator has stabilized, the internal reset signal is cleared and the CPU
starts reset exception handling.
6.2.4 Subactive Mode
The operating frequency of subactive mode is selected from φ_W/2, φ_W/4, and φ_W/8 by the SA1 and
SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to
the frequency which is set before the execution.
When the SLEEP instruction is executed in subactive mode, a transition to sleep mode, subsleep
mode, standby mode, active mode, or subactive mode is made, depending on the combination of
SYSCR1 and SYSCR2.
When the RES pin is driven low in standby mode, the on-chip oscillator starts functioning. Once
the oscillator starts, the system clock is supplied to the entire chip. The RES pin must be kept low
for the rated period set by the power-on reset circuit, until the oscillator stabilizes. If the RES pin
is driven high after the oscillator has stabilized, the internal reset signal is cleared and the CPU
starts reset exception handling.
Rev. 3.00 Sep. 10, 2007 Page 104 of 528
REJ09B0216-0300