HD64F3687GHV Datasheet, PDF (371/566 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 I²C Bus Interface 2 (IIC2)
Initial
Bit
Bit Name Value R/W Description
6
WAIT
0
R/W Wait Insertion Bit
In master mode with the I²C bus format, this bit selects
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of
the clock for the final data bit, low period is extended for
two transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no
wait inserted.
The setting of this bit is invalid in slave mode with the I²C
bus format or with the clock synchronous serial format.
5, 4 
All 1

Reserved
These bits are always read as 1, and cannot be modified.
3
BCWP 1
R/W BC Write Protect
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0 and
use the MOV instruction. In clock synchronous serial
mode, BC should not be modified.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
Rev. 3.00 Sep. 10, 2007 Page 337 of 528
REJ09B0216-0300