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MEGA128CAN Datasheet, PDF (90/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER | |||
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External Interrupt Mask
Register â EIMSK
External Interrupt Flag
Register â EIFR
Bit
Read/Write
Initial Value
7
INT7
R/W
0
6
INT6
R/W
0
5
INT5
R/W
0
4
INT4
R/W
0
3
INT3
R/W
0
2
INT2
R/W
0
1
INT1
R/W
0
0
IINT0
R/W
0
EIMSK
⢠Bits 7..0 â INT7 â INT0: External Interrupt Request 7 - 0 Enable
When an INT7 â INT0 bit is written to one and the I-bit in the Status Register (SREG) is
set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Con-
trol bits in the External Interrupt Control Registers â EICRA and EICRB â defines
whether the external interrupt is activated on rising or falling edge or level sensed. Activ-
ity on any of these pins will trigger an interrupt request even if the pin is enabled as an
output. This provides a way of generating a software interrupt.
Bit
Read/Write
Initial Value
7
INTF7
R/W
0
6
INTF6
R/W
0
5
INTF5
R/W
0
4
INTF4
R/W
0
3
INTF3
R/W
0
2
INTF2
R/W
0
1
INTF1
R/W
0
0
IINTF0
R/W
0
EIFR
⢠Bits 7..0 â INTF7 - INTF0: External Interrupt Flags 7 - 0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0
becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit,
INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by
writing a logical one to it. These flags are always cleared when INT7:0 are configured as
level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled,
the input buffers on these pins will be disabled. This may cause a logic change in inter-
nal signals which will set the INTF3:0 flags. See âDigital Input Enable and Sleep Modesâ
on page 65 for more information.
90 AT90CAN128
4250EâCANâ12/04
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