MEGA128CAN Datasheet, PDF (104/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

8-bit Timer/Counter
Register Description
Timer/Counter0 Control
Register A – TCCR0A
Figure 47 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Figure 47. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with
Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
(CTC)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
OCRnx
TOP
OCFnx
Bit
Read/Write
Initial Value
7
FOC0A
W
0
6
WGM00
R/W
0
5
COM0A1
R/W
0
4
COM0A0
R/W
0
3
WGM01
R/W
0
2
CS02
R/W
0
1
CS01
R/W
0
0
CS00
R/W
0
TCCR0
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. How-
ever, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0 is written when operating in PWM mode. When writing a logical one to the
FOC0A bit, an immediate compare match is forced on the Waveform Generation unit.
The OC0A output is changed according to its COM0A1:0 bits setting. Note that the
FOC0A bit is implemented as a strobe. Therefore it is the value present in the
COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum
(TOP) counter value, and what type of waveform generation to be used. Modes of oper-
ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare
match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table
54 and “Modes of Operation” on page 99.
104 AT90CAN128
4250E–CAN–12/04