MEGA128CAN Datasheet, PDF (251/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
CAN Bit Timing Register 1 -
CANBT1
CAN Bit Timing Register 2 -
CANBT2
• Bits 14:0 - SIT14:0: Status of Interrupt by MOb
–
–
Note:
0 - no interrupt.
1- MOb interrupt.
Example: CANSIT2 = 0010 0001_b : MOb 0 & 5 interrupts.
• Bit 15 – Reserved Bit
This bit is reserved for future use.
Bit
7
6
5
4
3
2
1
0
-
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
-
CANBT1
Read/Write
-
R/W
R/W
R/W
R/W
R/W
R/W
-
Initial Value
-
0
0
0
0
0
0
-
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, this must be writ-
ten to zero when CANBT1 is written.
• Bit 6:1 – BRP5:0: Baud Rate Prescaler
The period of the CAN controller system clock Tscl is programmable and determines the
individual bit timing.
BRP[5:0] + 1
Tscl =
clk_IO frequency
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, this must be writ-
ten to zero when CANBT1 is written.
Bit
7
6
5
4
3
2
1
0
-
SJW1 SJW0
-
PRS2
PRS1
PRS0
-
CANBT2
Read/Write
-
R/W
R/W
-
R/W
R/W
R/W
-
Initial Value
-
0
0
-
0
0
0
-
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, this must be writ-
ten to zero when CANBT2 is written.
• Bit 6:5 – SJW1:0: Re-Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus controllers, the
controller must re-synchronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit
period may be shortened or lengthened by a re-synchronization.
Tsjw = Tscl x (SJW [1:0] +1)
• Bit 4 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, this must be writ-
ten to zero when CANBT2 is written.
4250E–CAN–12/04
251