MEGA128CAN Datasheet, PDF (28/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0⁽¹⁾
T1
T2
T3
T4
T5
T6
System Clock (CLK_CPU)
ALE
A15:8 Prev. addr.
Address
DA7:0 Prev. data
Address XX
Data
WR
DA7:0 (XMBK = 0) Prev. data
Address
Data
DA7:0 (XMBK = 1) Prev. data
Address
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T6 is only present if the next instruction accesses the RAM
(internal or external).
Figure 17. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1⁽¹⁾
T1
System Clock (CLK_CPU)
ALE
A15:8 Prev. addr.
T2
T3
T4
T5
Address
T6
T7
DA7:0 Prev. data
Address XX
Data
WR
DA7:0 (XMBK = 0) Prev. data
Address
Data
DA7:0 (XMBK = 1) Prev. data
Address
Data
RD
XMEM Register Description
External Memory Control
Register A – XMCRA
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM
(internal or external).
Bit
Read/Write
Initial Value
7
SRE
R/W
0
6
SRL2
R/W
0
5
SRL1
R/W
0
4
SRL0
R/W
0
3
SRW11
R/W
0
2
SRW10
R/W
0
1
SRW01
R/W
0
0
SRW00
R/W
0
XMCRA
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,
A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit over-
28 AT90CAN128
4250E–CAN–12/04