MEGA128CAN Datasheet, PDF (351/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
including the first read byte. This ensures that the first data is captured from the first
address set up by PROG_COMMANDS, and reading the last location in the page
makes the program counter increment into the next page.
Figure 168. Flash Data Byte Register
STROBES
State
Machine
ADDRESS
TDI
Flash
EEPROM
Fuses
Lock Bits
D
A
T
A
Programming Algorithm
Entering Programming Mode
Leaving Programming Mode
Performing Chip Erase
4250E–CAN–12/04
TDO
The state machine controlling the Flash Data Byte Register is clocked by TCK. During
normal operation in which eight bits are shifted for each Flash byte, the clock cycles
needed to navigate through the TAP controller automatically feeds the state machine for
the Flash Data Byte Register with sufficient number of clock pulses to complete its oper-
ation transparently for the user. However, if too few bits are shifted between each
Update-DR state during page load, the TAP controller should stay in the Run-Test/Idle
state for some TCK cycles to ensure that there are at least 11 TCK cycles between each
Update-DR state.
All references below of type “1a”, “1b”, and so on, refer to Table 136.
1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.
2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Pro-
gramming Enable Register.
1. Enter JTAG instruction PROG_COMMANDS.
2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the
programming Enable Register.
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.
1. Enter JTAG instruction PROG_COMMANDS.
2. Start Chip Erase using programming instruction 1a.
3. Poll for Chip Erase complete using programming instruction 1b, or wait for
t_{WLRH_CE} (refer to Table 150 on page 372).
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