MEGA128CAN Datasheet, PDF (247/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
• Bit 0 – SWRES: Software Reset Request
This auto resettable bit only resets the CAN controller.
– 0 - no reset
– 1 - reset: this reset is “ORed” with the hardware reset.
CAN General Status Register -
CANGSTA
Bit
7
6
5
4
3
2
1
-
OVFG
-
TXBSY RXBSY ENFG BOFF
Read/Write
-
R
-
R
R
R
R
Initial Value
-
0
-
0
0
0
0
0
ERRP
R
0
CANGSTA
• Bit 7 – Reserved Bit
This bit is reserved for future use.
• Bit 6 – OVFG: Overload Frame Flag
This flag does not generate an interrupt.
– 0 - no overload frame.
– 1 - overload frame: set by hardware as long as the produced overload frame is
sent.
• Bit 5 – Reserved Bit
This bit is reserved for future use.
• Bit 4 – TXBSY: Transmitter Busy
This flag does not generate an interrupt.
– 0 - transmitter not busy.
– 1 - transmitter busy: set by hardware as long as a frame (data, remote, overload
or error frame) or an ACK field is sent. Also set when an inter frame space is
sent.
• Bit 3 – RXBSY: Receiver Busy
This flag does not generate an interrupt.
– 0 - receiver not busy
– 1 - receiver busy: set by hardware as long as a frame is received or monitored.
• Bit 2 – ENFG: Enable Flag
This flag does not generate an interrupt.
– 0 - CAN controller disable: because an enable/disable command is not
immediately effective, this status gives the true state of the chosen mode.
– 1 - CAN controller enable.
• Bit 1 – BOFF: Bus Off Mode
BOFF gives the information of the state of the CAN channel. Only entering in bus off
mode generates the BOFFIT interrupt.
– 0 - no bus off mode.
– 1 - bus off mode.
4250E–CAN–12/04
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