MEGA128CAN Datasheet, PDF (150/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

Timer/Counter Timing
Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock
(clk_T2) is therefore shown as a clock enable signal. In asynchronous mode, clk_I/O should
be replaced by the Timer/Counter Oscillator clock. The figures include information on
when interrupt flags are set. Figure 69 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 69. Timer/Counter Timing Diagram, no Prescaling
clk_I/O
clk_Tn
(clk_I/O/1)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
Figure 70 shows the same timing data, but with the prescaler enabled.
Figure 70. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
Figure 71 shows the setting of OCF2A in all modes except CTC mode.
Figure 71. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
150 AT90CAN128
4250E–CAN–12/04