MEGA128CAN Datasheet, PDF (285/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
Figure 141. Block Diagram
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –
which is not provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins
and the TAP controller is in reset. When programmed and the JTD bit in MCUCR is
cleared, the TAP input signals are internally pulled high and the JTAG is enabled for
Boundary-scan and programming. In this case, the TAP output pin (TDO) is left floating
in states where the JTAG TAP controller is not shifting data, and must therefore be con
nected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-input
of the next device in the scan chain). The device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is
monitored by the debugger to be able to detect external reset sources. The debugger
can also pull the RESET pin low to reset the whole system, assuming only open collec-
tors on the reset line are used in the application.
I/O PORT 0
DEVICE BOUNDARY
BOUNDARY SCAN CHAIN
TDI
TDO
TCK
TMS
TAP
CONTROLLER
INSTRUCTION
REGISTER
ID
REGISTER
M
U
BYPASS
X
REGISTER
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
JTAG PROGRAMMING
INTERFACE
FLASH Address
MEMORY
Data
BREAKPOINT
UNIT
INTERNAL
SCAN
CHAIN
PC
Instruction
AVR CPU
FLOW CONTROL
UNIT
DIGITAL
PERIPHERAL
UNITS
OCD STATUS
AND CONTROL
JTAG / AVR CORE
COMMUNICATION
INTERFACE
ANALOG
PERIPHERIAL
UNITS
4250E–CAN–12/04
I/O PORT n
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