MEGA128CAN Datasheet, PDF (191/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
USART1 Control and Status
Register B – UCSR1B
USART0 Control and Status
Register C – UCSR0C
Bit
Read/Write
Initial Value
7
RXCIE1
R/W
0
6
TXCIE1
R/W
0
5
UDRIE1
R/W
0
4
RXEN1
R/W
0
3
TXEN1
R/W
0
2
UCSZ12
R/W
0
1
RXB81
R
0
0
TXB81
R/W
0
UCSR1B
• Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn flag. A USARTn Receive Complete
interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXCn bit in UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn flag. A USARTn Transmit Complete
interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXCn bit in UCSRnA is set.
• Bit 5 – UDRIEn: USARTn Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn flag. A Data Register Empty inter-
rupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USARTn Receiver. The Receiver will override normal
port operation for the RxDn pin when enabled. Disabling the Receiver will flush the
receive buffer invalidating the FEn, DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USARTn Transmitter. The Transmitter will override
normal port operation for the TxDn pin when enabled. The disabling of the Transmitter
(writing TXENn to zero) will not become effective until ongoing and pending transmis-
sions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register
do not contain data to be transmitted. When disabled, the Transmitter will no longer
override the TxDn port.
• Bit 2 – UCSZn2: Character Size
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data
bits (Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames
with nine data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the ninth data bit in the character to be transmitted when operating with serial
frames with nine data bits. Must be written before writing the low bits to UDRn.
Bit
Read/Write
7
6
5
4
3
2
1
0
–
UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 UCSR0C
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4250E–CAN–12/04
191