MEGA128CAN Datasheet, PDF (337/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
SPI Serial Programming This section describes how to serial program and verify Flash Program memory,
Overview
EEPROM Data memory, Memory Lock bits, and Fuse bits in the AT90CAN128.
Signal Names
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
Table 133 on page 338, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface. Note that throughout the descrip-
tion about Serial downloading, MOSI and MISO are used to describe the serial data in
and serial data out respectively. For AT90CAN128 these pins are mapped to PDI (PE0)
and PDO (PE1).
Figure 162. Serial Programming and Verify⁽¹⁾
PDI
PE0
PDO
PE1
SCK
PB1
+2.7 - +5.5V
VCC
+2.7 - +5.5V
AVCC
XTAL1
RESET
GND
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock
source to the XTAL1 pin.
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the Serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and
high periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f_ck < 12 MHz, 3 CPU clock cycles for f_ck ≥ 12 MHz
High: > 2 CPU clock cycles for f_ck < 12 MHz, 3 CPU clock cycles for f_ck ≥ 12 MHz
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