MEGA128CAN Datasheet, PDF (292/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

put from this data register is not latched, so the reset will take place immediately, as
shown in Figure 144.
Figure 144. Reset Register
From Other Internal and
External Reset Sources
Internal reset
From TDI
DQ
To TDO
ClockDR · AVR_RESET
Boundary-scan Chain
The Boundary-scan Chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having off-chip connections.
See “Boundary-scan Chain” on page 294 for a complete description.
Boundary-scan Specific
JTAG Instructions
The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are
the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ
instruction is not implemented, but all outputs with tri-state capability can be set in high-
impedant state by using the AVR_RESET instruction, since the initial state for all port
pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format.
The text describes which data register is selected as path between TDI and TDO for
each instruction.
EXTEST (0x0)
Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register for
testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output
Control, Output Data, and Input Data are all accessible in the scan chain. For Analog cir-
cuits having off-chip connections, the interface between the analog and the digital logic
is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is
driven out as soon as the JTAG IR-Register is loaded with the EXTEST instruction.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
IDCODE (0x1)
Optional JTAG instruction selecting the 32 bit ID-Register as data register. The ID-Reg-
ister consists of a version number, a device number and the manufacturer code chosen
by JEDEC. This is the default instruction after power-up.
The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan
Chain.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
292 AT90CAN128
4250E–CAN–12/04