MEGA128CAN Datasheet, PDF (300/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

Scanning the ADC
Figure 152 shows a block diagram of the ADC with all relevant control and observe sig-
nals. The Boundary-scan cell from Figure 151 is attached to each of these signals. The
ADC need not be used for pure connectivity testing, since all analog inputs are shared
with a digital port pin as well.
Figure 152. Analog to Digital Converter
MUXEN_7
ADC_7
MUXEN_6
ADC_6
MUXEN_5
ADC_5
MUXEN_4
ADC_4
EXTCH
MUXEN_3
ADC_3
MUXEN_2
ADC_2
MUXEN_1
ADC_1
MUXEN_0
ADC_0
NEGSEL_2
ADC_2
NEGSEL_1
ADC_1
NEGSEL_0
ADC_0
VCCREN
AREF
IREFEN
To Comparator
2.56V
ref
PASSEN
SCTEST
ADCBGEN
1.22V
ref
G10
+
10x
-
ST
ACLK
AMPEN
G20
ACTEN
+
20x
-
GNDEN
ADHSM
PRECH
ADHSM
PRECH
AREF
DAC_9..0
10-bit DAC
ADCEN
HOLD
DACOUT
+
COMP
-
The signals are described briefly in Table 111.
Table 111. Boundary-scan Signals for the ADC⁽¹⁾
Signal
Name
Direction
as Seen
from the
ADC
Description
Recommen-
ded Input
when not
in Use
COMP
Output
Comparator Output
0
ACLK
Input
Clock signal to gain
0
stages implemented
as Switch-cap filters
ACTEN
Input
Enable path from gain
0
stages to the
comparator
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC
0
0
0
300 AT90CAN128
4250E–CAN–12/04