MEGA128CAN Datasheet, PDF (329/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
Parallel Programming
Overview
Signal Names
This section describes how to parallel program and verify Flash Program memory,
EEPROM Data memory, Memory Lock bits, and Fuse bits in the AT90CAN128. Pulses
are assumed to be at least 250 ns unless otherwise noted.
In this section, some pins of the AT90CAN128 are referenced by signal names describ-
ing their functionality during parallel programming, see Figure 156 and Table 127. Pins
not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-
tive pulse. The bit coding is shown in Table 129.
When pulsing WR or OE, the command loaded determines the action executed. The dif-
ferent Commands are shown in Table 130.
Figure 156. Parallel Programming
RDY/BSY
OE
WR
BS1
XA0
XA1
PAGEL
+12 V
BS2
PD1
PD2
PD3
PD4
PD5
PD6
PD7
RESET
PA0
XTAL1
GND
+2.7 - +5.5V
VCC
+2.7 - +5.5V
AVCC
PB7 - PB0
DATA
Pin Mapping
4250E–CAN–12/04
Table 127. Pin Name Mapping
Signal Name in
Programming Mode Pin Name I/O Function
RDY/BSY
PD1
O
0: Device is busy programming,
1: Device is ready for new command.
OE
PD2
I Output Enable (Active low).
WR
PD3
I Write Pulse (Active low).
BS1
PD4
I
Byte Select 1
(“0” selects low byte, “1” selects high byte).
XA0
PD5
I XTAL Action Bit 0
XA1
PD6
I XTAL Action Bit 1
PAGEL
PD7
I Program Memory and EEPROM data Page Load.
BS2
PA0
I
Byte Select 2
(“0” selects low byte, “1” selects 2’nd high byte).
DATA
PB7-0 I/O Bi-directional Data bus (Output when OE is low).
329