MEGA128CAN Datasheet, PDF (136/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

Output Compare Register A –
OCR1AH and OCR1AL
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR1A[15:8]
OCR1AH
OCR1A[7:0]
OCR1AL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Output Compare Register B –
OCR1BH and OCR1BL
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR1B[15:8]
OCR1BH
OCR1B[7:0]
OCR1BL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Output Compare Register C –
OCR1CH and OCR1CL
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR1C[15:8]
OCR1CH
OCR1C[7:0]
OCR1CL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Output Compare Register A –
OCR3AH and OCR3AL
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR3A[15:8]
OCR3AH
OCR3A[7:0]
OCR3AL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Output Compare Register B –
OCR3BH and OCR3BL
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR3B[15:8]
OCR3BH
OCR3B[7:0]
OCR3BL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Output Compare Register C –
OCR3CH and OCR3CL
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR3C[15:8]
OCR3CH
OCR3C[7:0]
OCR3CL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNTn). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is
performed using an 8-bit temporary high byte register (TEMP). This temporary register
is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 111
Input Capture Register –
ICR1H and ICR1L
Bit
Read/Write
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
136 AT90CAN128
4250E–CAN–12/04