MEGA128CAN Datasheet, PDF (13/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
Instruction Execution
Timing
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock
source for the chip. No internal clock division is used.
Figure 7 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 7. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clk_CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 8 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Figure 8. Single Cycle ALU Operation
T1
T2
T3
T4
clk_CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
Reset and Interrupt
Handling
4250E–CAN–12/04
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
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