MEGA128CAN Datasheet, PDF (35/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
ADC Clock – clk_ADC
Clock Sources
Default Clock Source
domain allows using this Timer/Counter as a real-time counter even when the device is
in sleep mode.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accu-
rate ADC conversion results.
The device has the following clock source options, selectable by Flash Fuse bits as
shown below. The clock from the selected source is input to the AVR clock generator,
and routed to the appropriate modules.
Table 5. Device Clocking Options Select⁽¹⁾
Device Clocking Option
CKSEL3..0
External Crystal/Ceramic Resonator
1111 - 1000
External Low-frequency Crystal
0111 - 0100
Calibrated Internal RC Oscillator
0010
External Clock
0000
Reserved
0011, 0001
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the
CPU wakes up from Power-down or Power-save, the selected clock source is used to
time the start-up, ensuring stable Oscillator operation before instruction execution starts.
When the CPU starts from reset, there is an additional delay allowing the power to reach
a stable level before starting normal operation. The Watchdog Oscillator is used for tim-
ing this real-time part of the start-up time. The number of WDT Oscillator cycles used for
each time-out is shown in Table 6. The frequency of the Watchdog Oscillator is voltage
dependent as shown in “AT90CAN128 Typical Characteristics” on page 374.
Table 6. Number of Watchdog Oscillator Cycles
Typ Time-out (V_CC = 5.0V)
4.1 ms
Typ Time-out (V_CC = 3.0V)
4.3 ms
65 ms
69 ms
Number of Cycles
4K (4,096)
64K (65,536)
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed.
The default clock source setting is the Internal RC Oscillator with longest start-up time
and an initial system clock prescaling of 8. This default setting ensures that all users can
make their desired clock source setting using an In-System or Parallel programmer.
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