MEGA128CAN Datasheet, PDF(174/413 Page) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

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MEGA128CAN Datasheet, PDF (174/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

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machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn,

U2Xn and DDR_XCKn bits.

Table 76 contains equations for calculating the baud rate (in bits per second) and for

calculating the UBRRn value for each mode of operation using an internally generated

clock source.

Table 76. Equations for Calculating Baud Rate Register Setting

Operating Mode

Equation for Calculating

Baud Rate(1)

Equation for Calculating

UBRRn Value

Asynchronous Normal

mode (U2Xn = 0)

BAUD = -1---6---(---U----f-BC----RL---K-R---i-o-n----+-----1----)

UBRRn = 1----6f--C-B---L-A--K--U--i-o--D--- â 1

Asynchronous Double

Speed mode (U2Xn = 1)

BAUD = -8---(---U----B-f--C--R-L---RK----in--o---+-----1----)

UBRRn = 8---f-B-C---AL---K-U---i--oD--- â 1

Synchronous Master

mode

BAUD = -2---(---U----B-f--C--R-L---RK----in--o---+-----1----)

UBRRn = 2---f-B-C---AL---K-U---i--oD--- â 1

Double Speed Operation

(U2X)

External Clock

Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

fclkio

UBRRn

Baud rate (in bits per second, bps).

System I/O Clock frequency.

Contents of the UBRRnH and UBRRnL Registers, (0-4095).

Some examples of UBRRn values for some system clock frequencies are found in Table

84 (see page 195).

The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit

only has effect for the asynchronous operation. Set this bit to zero when using synchro-

nous operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively

doubling the transfer rate for asynchronous communication. Note however that the

Receiver will in this case only use half the number of samples (reduced from 16 to 8) for

data sampling and clock recovery, and therefore a more accurate baud rate setting and

system clock are required when this mode is used. For the Transmitter, there are no

downsides.

External clocking is used by the synchronous slave modes of operation. The description

in this section refers to Figure 84 for details.

External clock input from the XCKn pin is sampled by a synchronization register to mini-

mize the chance of meta-stability. The output from the synchronization register must

then pass through an edge detector before it can be used by the Transmitter and

Receiver. This process introduces a two CPU clock period delay and therefore the max-

imum external XCKn clock frequency is limited by the following equation:

fXCKn < -f-C----L-4--K----i-o-

Note that fclkio depends on the stability of the system clock source. It is therefore recom-

mended to add some margin to avoid possible loss of data due to frequency variations.

174 AT90CAN128

4250EâCANâ12/04

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