MEGA128CAN Datasheet, PDF (321/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in
the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destina-
tion register as shown below. Refer to Table 124 on page 326 for detailed description
and mapping of the Extended Fuse byte.
Bit
7
6
5
4
3
2
1
0
Rd (Z=0x0002)
–
–
–
–
EFB3
EFB2
EFB1
EFB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that
are unprogrammed, will be read as one.
Preventing Flash Corruption
During periods of low V_CC, the Flash program can be corrupted because the supply volt-
age is too low for the CPU and the Flash to operate properly. These issues are the same
as for board level systems using the Flash, and the same design solutions should be
applied.
A Flash program corruption can be caused by two situations when the voltage is too low.
• First, a regular write sequence to the Flash requires a minimum voltage to operate
correctly.
• Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage
for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one
is sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot
Loader Lock bits to prevent any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply
voltage. This can be done by enabling the internal Brown-out Detector (BOD) if
the operating voltage matches the detection level. If not, an external low V_CC
reset protection circuit can be used. If a reset occurs while a write operation is in
progress, the write operation will be completed provided that the power supply
voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This
will prevent the CPU from attempting to decode and execute instructions, effec-
tively protecting the SPMCSR Register and thus the Flash from unintentional
writes.
Programming Time for Flash
when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 118 shows the typi-
cal programming time for Flash accesses from the CPU.
Table 118. SPM Programming Time
Symbol
Min Programming Time Max Programming Time
Flash write (Page Erase, Page Write,
and write Lock bits by SPM)
3.7 ms
4.5 ms
Simple Assembly Code
Example for a Boot Loader
;- the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y-pointer
; the first data location in Flash is pointed to by the Z-pointer
;- error handling is not included
;- the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;- registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
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