MEGA128CAN Datasheet, PDF (133/413 Pages) ATMEL Corporation – Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER

AT90CAN128
match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See
“Modes of Operation” on page 121 ).
Table 63. Waveform Generation Mode Bit Description⁽¹⁾
WGMn2 WGMn1 WGMn0 Timer/Counter Mode of
Mode WGMn3 (CTCn) (PWMn1) (PWMn0) Operation
TOP
Update of
OCRnx at
TOVn Flag
Set on
0
0
0
0
0
Normal
0xFFFF Immediate
MAX
1
0
0
0
1
PWM, Phase Correct, 8-bit 0x00FF TOP
BOTTOM
2
0
0
1
0
PWM, Phase Correct, 9-bit 0x01FF TOP
BOTTOM
3
0
0
1
1
PWM, Phase Correct, 10- 0x03FF TOP
bit
BOTTOM
4
0
1
0
0
CTC
OCRnA Immediate
MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF TOP
TOP
6
0
1
1
0
Fast PWM, 9-bit
0x01FF TOP
TOP
7
0
1
1
1
Fast PWM, 10-bit
0x03FF TOP
TOP
8
1
0
0
0
PWM, Phase and
Frequency Correct
ICRn
BOTTOM
BOTTOM
9
1
0
0
1
PWM, Phase and
Frequency Correct
OCRnA BOTTOM
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICRn
TOP
BOTTOM
11
1
0
1
1
PWM, Phase Correct
OCRnA TOP
BOTTOM
12
1
1
0
0
CTC
ICRn
Immediate
MAX
13
1
1
0
1
(Reserved)
–
–
–
14
1
1
1
0
Fast PWM
ICRn
TOP
TOP
15
Note:
1
1
1
1
Fast PWM
OCRnA TOP
TOP
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
Timer/Counter1 Control
Register B – TCCR1B
Bit
Read/Write
Initial Value
7
ICNC1
R/W
0
6
ICES1
R/W
0
5
4
3
2
1
0
–
WGM13 WGM12 CS12
CS11
CS10 TCCR1B
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Timer/Counter3 Control
Register B – TCCR3B
Bit
Read/Write
Initial Value
7
ICNC3
R/W
0
6
ICES3
R/W
0
5
4
3
2
1
0
–
WGM33 WGM32 CS32
CS31
CS30 TCCR3B
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise can-
celer is activated, the input from the Input Capture pin (ICPn) is filtered. The filter
function requires four successive equal valued samples of the ICPn pin for changing its
output. The Input Capture is therefore delayed by four Oscillator cycles when the noise
canceler is enabled.
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